1. Field of the Invention
The present invention relates to a method of timing optimization of an integrated circuit, and more particularly, to a method of efficiently calculating timing yield criticality, which is newly defined for effectively determining nodes significantly affecting a timing yield of an integrated circuit, for statistical timing optimization of integrated circuits.
2. Description of the Related Art
In fabrication of very-large-scale-integration (VLSI) circuits, variations in chip performance become more significant due to variations in the manufacturing process, which is increased as fabrication techniques become more intricate, and thus a loss in chip yield becomes a serious problem. Examples of conventional methods of analyzing timing in consideration of the process variation include corner-based static timing analysis and Monte-Carlo simulation-based static timing analysis. According to the corner-based static timing analysis, a timing variation in a chip is predicted based on analysis at a couple of important process corners, such as in the case of the best parameter conditions affecting improvement in the chip's operating speed, the case of the worst parameter conditions, and the case of normal parameter conditions. The method of analysis may significantly overrate the effect of process variations with respect to chip timing in a current nanometer process in which both process variations between chips and process variations within a chip significantly affect chip performance.
According to the other conventional method of analyzing timing, that is, the Monte-Carlo simulation-based static timing analysis, a highly accurate analysis result can be obtained. However, calculation thereof is highly complicated, and thus it is practically impossible to apply the method to actual chip design.
As an alternative to such conventional analyzing methods, statistical static timing analysis (SSTA) has been suggested. According to the SSTA, timings of a chip are indicated as a probability distribution, and timing yield, which is a probability that a chip satisfies given timing-limiting conditions, is predicted based on the distribution of probabilities. SSTA can be roughly classified into path-based SSTA and block-based SSTA. According to the path-based SSTA, a timing distribution of a chip is predicted by analyzing timings of potential critical paths that are selected in advance.
In conventional static timing analysis, a critical path has the longest delay from among all paths, and thus can be easily confirmed. Meanwhile, in SSTA, delays of all circuit components are indicated by random variables, and every path has a probability of becoming a critical path. Thus, a new method, which is different from the method used in static timing analysis (STA), is required to determine a critical path in SSTA.
References regarding conventional techniques to which SSTA is applied are shown below.
Reference 1: C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, D. K. Beece, J. Piaget, N. Venkateswaran, and J. G. Hemmett, “First-order incremental block-based statistical timing analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 2170-2180, October 2006.
Reference 2: X. Li, J. Le, M. Celik, and L. T. Pileggi, “Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations,” Proc. International Conf. on Computer-Aided Design, pp. 844-851, November 2005.
Timing analysis regarding a digital circuit is performed in the timing graph shown in FIG. 1, for example. In order to simplify timing analysis regarding a circuit, primary input nodes 1, 2, 3, and 4 of the timing graph and primary output nodes 9 and 10 of the timing graph are connected to a virtual source node 100 and a virtual sink node 110, respectively. The virtual source node 100 becomes the origin of all circuit signals, whereas the virtual sink nodes 110 becomes the final destination of all circuit signals.
In general digital circuits, input pins and output pins of gates are converted to nodes corresponding to each of the pins. Signal paths from input pins to output pins of gates and delays thereof are converted to edges between nodes and to edge delays, respectively. Furthermore, connecting lines between gates and delays thereof are also converted to edges and edge delays, respectively.
In the reference 1, timing criticalities of paths, nodes, and edges are defined using tightness probability. In the reference 1, path criticality indicates a probability that a corresponding path has the longest delay, whereas node/edge criticalities indicate corresponding node/edge are located on a critical path.
In the reference 2, sensitivities of paths and arcs, which are defined by the sensitivity of mean arrival time at a virtual sink node, with respect to mean delay of paths or arcs, are suggested for timing criticality. Sensitivities of paths and arcs represent a probability that a corresponding path becomes a critical path and a probability that a corresponding arc is located on the critical path, respectively, which are similar to criticalities of paths and edges. Thus, the most critical path based on timing criticalities suggested in the references 1 and 2 is a path having the highest probability that the path becomes a critical path, and the most critical node/edges are a node and an edge that have the highest probability that the path becomes a critical node and a critical edge, respectively.
In SSTA, delays of all gates affect timing yield of chips, and optimization of timing yield is achieved by gate replacement. Therefore, node/edge timing criticalities should be defined in a timing graph to determine gates significantly affecting timing yield.
However, conventional timing criticalities suggested in references 1 and 2 are not defined in view of timing yield, and thus there are cases where the most critical node/edge predicted based on the definitions of references 1 and 2 are not node/edge affecting the timing yield most significantly, in reality.